1. Field of the Invention
The present invention relates to a semiconductor device comprising a high density integrated circuit having a large number of insulated gate field effect transistors, and more particularly relates to a semiconductor device aiming at high density integration of transistors while reducing effects of the contact resistance against the transistor performance.
2. Description of the Related Art
Because of improvement in integration density due to the minimization of semiconductor elements, the memory capacity of dynamic random access memory (DRAM) for example, has increased by four times in three years. It is needless to say that the area of a memory cell for storing information has been reduced by minimizing the size of an element. Improvement in the aforementioned integration has been achieved, by reducing also the size of an element used for a peripheral circuit for writing and reading information stored in a memory cell.
One of the important peripheral circuits of DRAM is a sense amplifier. FIG. 1 is a circuit diagram showing a typical sense amplifier, which is a shared sense amplifier of folded bit line structure. A sense amplifier includes a pair of bit lines BLa and BLb, which extend to memory cell array region 251a and 251b on the both sides of the sense amplifier. Respective bit lines BLa and BLb are connected with input/output lines I/Oa and I/Ob through a transistor which serves as a switch.
Also provided are transfer gate TG for selecting one of the cell array memory regions, PDL and HVCD connected with a bit line equalizer circuit, and amplifier circuit 254. Amplifier circuit 254, in which inputs and outputs of the two CMOS inverters consisting of N channel transistors 252a, 252b and P channel transistors 253a, 253b cross each other, is connected with bit lines BLa and BLb. A flip-flop consisting of the N channel transistor is connected with sense amplifier driving line SAN, while a flip-flop consisting of the P channel transistor is connected with sense amplifier driving line SAP.
The sense amplifier is required to have a function for detecting a small potential difference which is readout to one of the bit lines by the electric charge stored in the memory cell. The crucial point for obtaining a high performance sense amplifier is that the bit line capacity of pair of bit lines BLa and BLb, performance of elements connected with the bit lines and their resistance of wiring and contact are equal. Among others, it is important that the balance of performance of the pair of transistors constituting amplifier circuit 254 are equal to each other.
Therefore, it is desirable to make the shape and layout of component patterns constituting a pair of bit lines and elements to be connected with the bit lines equal. FIG. 2 shows the layout pattern of typical amplifier circuit 254. Since the sense amplifiers are arrayed in accordance with the memory cell array, patterns for the four amplifiers are shown to facilitate the explanation of the layout pattern. The amplifier circuit shown in FIG. 2 has a structure of shared sense amplifier. The pattern width of amplifier circuit 254 is twice the pattern width of the memory cell, that is, the pitch of the bit line of amplifier circuit 254 is twice the pitch of the bit line of the memory cell.
Hereinafter, the structure of the amplifier circuit will be described in detail. As for the size of each pattern, the size of first generation 256 DRAM of minimum design dimensions 0.25 xcexcm is given as an example. In general, the design dimensions of a peripheral circuit region is set in values larger than those of the minimum design dimensions used in the memory cell array region. The pitch of the bit line of the memory cell is 0.6 xcexcm. The pitch of the bit line of the sense amplifier region is 1.2 xcexcm, and the width of one amplifier circuit is 2.4 xcexcm.
As shown in FIG. 3, a P well 204 is formed in N channel transistor region 201 on the surface of P-type silicon substrate 203, and N well 205 is formed in P channel transistor region 202. Two regions 204 and 205 are separated by field oxide film 206 formed with the ordinary selective oxidation method.
In the region where a transistor is formed except for the region of field oxide film 206, gate oxide film 207 is formed. In the desired region on the surface of gate oxide film 207 and field oxide film 206, formed are N gate electrode 208 and P gate electrode 209 which serve as gate electrodes of the N channel transistor and the P channel transistor, each having width 0.7 xcexcm and consisting of an N-type polycrystalline silicon layer.
On the surface of P well 204 except for the region in which field oxide film 206 and N gate electrode 208 are formed, N-type diffusion layer 210 which serves as a source drain of the N channel transistor is formed. On the surface of N well 205 except for the region in which field oxide film 206 and P gate electrode 209 are formed, P-type diffusion layer 211 which serves as a source drain of the P channel transistor is formed.
In the desired region in inter-layer insulation film 219, formed are N drain contact 212 having diameter of 0.4 xcexcm and connecting N-type diffusion layer 210 which serves as a drain of the N channel transistor and bit line 216, N gate contact 214 having diameter of 0.4 xcexcm and connecting N gate electrode 208 and bit line 216, P drain contact 213 having diameter of 0.4 xcexcm and connecting P-type diffusion layer 211 which serves as a drain of the P channel transistor and bit line 216, and P gate contact 215 having diameter of 0.4 xcexcm and connecting P gate electrode 209 and bit line 216.
In the above, each of N drain contact 212, N gate contact 214, P drain contact 213 and P gate contact 215 are formed of a contact plug embedded with barrier metal consisting of TiN/Ti and tungsten. In a desired region of inter-layer insulation film 219, formed are N source contact 212 having diameter of 0.4 xcexcm which is used in common in the two N channel transistors and connecting N-type diffusion layer 210 which serves as a common source of the two N channel transistors and SAN wiring 220, and a P source contact having diameter of 0.4 xcexcm which is used in common in the two P channel transistors and connecting P-type diffusion layer 211 which serves as a common source of the two P channel transistors and SAP wiring 221. Each of N source contact 217 and P source contact 218 are formed of a contact plug embedded with barrier metal consisting of TiN/Ti and tungsten.
Integration of a semiconductor device has been carried out by reducing the size of elements in accordance with the scaling rule. In order to explain the effects of parasitic resistance which cause troubles when elements are reduced in size, the components constituting a transistor and resistors in the current path of the transistor are shown in FIG. 4. According to the scaling rule, in a constant electric field where the voltage drops in proportion to a decrease in the element size, channel resistance Rch of the transistor is kept constant. On the other hand, resistance of a parasitic component such as a contact or wiring increases when the size is decreased. For example, wiring resistance (Rws, Rwd), plug resistance (Rps, Rpd) connecting the wiring and the diffusion layer and diffusion layer resistance (Rds, Rdd) increase inversely with the scaling down. Contact resistance (Rcs, Rcd) between the plug and the diffusion layer, which increases inversely with the contact area, increases in inverse square of the diameter of the contact.
When an element has larger dimensions (e.g., larger than 1 xcexcm), since the aforementioned parasitic resistance has a sufficiently small value compared with that of the channel resistance, it has little influence over the current driving capability of the transistor. When the element is minimized to 0.5 xcexcm or smaller, however, the parasitic resistance, the contact resistance against the channel resistance in particular, increases to a value too large to be neglected.
FIG. 5 shows, as an example, the relationship between the contact diameter and the contact resistor embedded with TiN/Ti barrier metal and tungsten connecting the N-type diffusion layer and an aluminum electrode. When the contact diameter reaches 0.4 xcexcm, the contact resistance increases to scores of xcexa9, and besides, the standard deviation indicating the extent of variation increases. The increase in the contact resistance due to the reduction in contact diameter and the variation cause a decrease in the drain current and an increase in its standard deviation as seen in FIG. 6, namely, affect the current driving capability of the transistor. Besides, the amount of decrease in the current driving capability is larger than the value expected with the increase in the contact resistance.
When current Id runs through the N channel transistor, for example, due to an Ixe2x80xa2R drop caused by the parasitic resistance (mainly the contact resistance Rcs or Rcd), the voltage at the source and the drain of the transistor changes due to the voltage supplied from the outside. In the case of the N channel transistor, wherein the voltage supplied to an external source terminal, a drain terminal, a gate terminal and a substrate terminal are given as Vs, Vd, Vg and Vb respectively (Vd greater than Vs), the source potential and the drain potential within the N transistor is given as
Vs+Idxe2x80xa2Rcs and Vdxe2x88x92Idxe2x80xa2Rcd. 
In general, electric current does not run through a gate terminal and a substrate terminal, within the operation range of a transistor in a normal stationary state. Therefore, Vg and Vb are the same values within the transistor. However, since the gate potential and the substrate potential which have significance in the transistor characteristic are potential with respect to the source potential serving as a standard potential, actual gate potential and substrate potential are expressed in equations:
Vgs=Vgxe2x88x92(Vs+Idxe2x80xa2Rcs);
and
Vbs=Vbxe2x88x92(Vs+Idxe2x80xa2Rcs).
This means that the gate potential and the substrate potential decrease. Therefore, the drain current running through the transistor may decrease due to a change in the standard source potential, as well as in the parasitic contact resistance.
Namely, the first problem to be solved is that in the case of current driving capability of a transistor of 0.5 xcexcm or smaller in size, the parasitic source contact resistance on the source side and an increase in variation thereof may cause a drop in the current driving capability of the transistor and an increase in variation of the transistor characteristic.
The second problem to be solved is that the unbalance in the transistor characteristic due to the variation in the contact resistance may deteriorate the performance of a flip-flop circuit, and decrease the reliability in the integrated circuit.
It is an object of the present invention to provide a semiconductor device comprising a high density integrated circuit having a large number of insulated gate field effect transistors with improved performance of the transistors of minimum size and with improved uniformity in performance thereof.
In order to achieve the object above, a semiconductor device according to the present invention is a semiconductor device comprising a high density integrated circuit having a large number of insulated gate field effect transistors wherein the source contact resistance is smaller than the drain contact resistance.
The above insulated gate field effect transistors are used to form pairs of transistors in a flip-flop circuit.
Each of the above insulated gate field effect transistors has a diameter larger than that of the drain contact.
Each of the above insulated gate field effect transistors has a silicide layer formed only on its diffusion layer which is to serves as a source thereof, while silicide layer is not formed on the diffusion layer which is to serve as a drain.
In the above insulated gate field effect transistor, the material connecting the source contact plug and the diffusion layer is different from the material used for connecting the drain contact plug and the diffusion layer.
According to the semiconductor device of the present invention, the source contact resistance of the transistor is lower than the drain contact resistance thereof. Therefore, increase in the transistor current driving capability and uniformity in the transistor characteristic can be accomplished while high density integration is also achieved. As a result, the operation of the integrated circuit using a flip-flop amplifier circuit is stabilized.
The above and the other object, features, and advantages of the present invention will become apparent from the following description based on the accompanying drawings which illustrate an example of a preferred embodiment of the present invention.